A Software-Defined AI/HPC Rack-Scale Emulation Platform
With an early-stage experimental Hyperscale Data Center Facility Twin
Four programmes, each built from scratch and developed the way the Linux kernel is: a rack-scale emulation platform, a computer architecture, an in-kernel execution engine, and a secure packet-processing system on chip. Each is open source, and each is at a different point on the road to publication.
A Software-Defined AI/HPC Rack-Scale Emulation Platform
With an early-stage experimental Hyperscale Data Center Facility Twin
Incarnation of DEC PDP-11 into RISC-V
An experimental 64-bit general-purpose computer architecture for Agentic Infrastructure
A RISC-V ISA In-Kernel Bytecode JIT VM
RISC-V Pass-through Native ISA, JIT VM Translation, and FPGA Soft-core
Keystone Enclave Secured TRusted eBPF Logic on RISC-V - PCIe Accelerator
Mitigating Cross-Tenant Slot-Memory Access and Over-Broad Host-Memory DMA
All four projects are under active research and release preparation. Source repositories, upstream contribution series, publications, research data, and reproducibility artifacts are not yet publicly available. Each project's availability page carries the status of every item and is updated as each becomes public.
For collaboration, or to be notified when artifacts are released, please get in touch.