HiGPU, Datasheet
Part: higpu ·
Type: SIMT virtual GPU accelerator ·
Version: `v0.2.0-3-g4104982` ·
Repo: PacketFive/HiGPU
1. Overview
HiGPU is the emulated GPU accelerator of the HiCAIN platform. It presents a
QEMU PCIe device with a SIMT (single-instruction, multiple-thread) execution
model, a portable HiIR instruction set, and a CUDA-style runtime
(libhicart). Kernels are dispatched to the best available host SIMD backend
(AVX-512, AVX2, or scalar) selected at runtime, giving GPU-like compute on
commodity CPUs.
Key features
- SIMT execution model with 32-thread warps.
- HiIR portable ISA (RVV 1.0 subset plus HiCAIN tensor opcodes).
- Multi-architecture compute backends with runtime dispatch and env-var override.
- CUDA-style runtime (
libhicart) over a low-level driver shim (libhi).
- Tensor MAC unit per SM for matmul / AI workloads.
- Native HiLink endpoint for GPU-to-GPU fabric traffic.
hicasmi / hi-smi inventory and telemetry.
2. Device block diagram
flowchart TB
subgraph GPU["higpu device (default config)"]
direction TB
subgraph SMS["16 x Streaming Multiprocessor (SM)"]
direction LR
SM0["SM: 32 ALU lanes<br/>1 tensor MAC<br/>1 warp sched<br/>1 SFU<br/>64 KB regfile<br/>128 KB L1/shared"]
end
L2["L2 cache (8 MB)"]
HBM["Device memory (8 GB, HBM model)"]
LINK["HiLink endpoint (4 lanes)"]
SMS --> L2 --> HBM
SMS --> LINK
end
subgraph BARS["PCIe BARs"]
direction LR
BAR0["BAR0: 64 KB MMIO regs"]
BAR1["BAR1: device mem window (<=16 GB)"]
BAR2["BAR2: 4 KB doorbell pages"]
end
BARS --- GPU
classDef s fill:#fce7f3,stroke:#9d174d,color:#831843
classDef m fill:#dbeafe,stroke:#1e40af,color:#1e3a8a
class SM0,SMS s
class L2,HBM,LINK,BAR0,BAR1,BAR2 m
3. Functional specifications
| Parameter |
Value |
| PCI vendor : device ID |
0x1ED5 : 0xCA20 |
| Execution model |
SIMT, 32-thread warps |
| ISA |
HiIR (RVV 1.0 subset + tensor opcodes) |
| Streaming Multiprocessors (SM) |
16 (default configuration) |
| Vector ALU lanes / SM |
32 |
| Tensor MAC units / SM |
1 |
| Warp schedulers / SM |
1 |
| Special function units / SM |
1 |
| Register file / SM |
64 KB (~1 cycle) |
| L1 / shared memory / SM |
128 KB (~30 cycles) |
| L2 cache (chip-wide) |
8 MB (~200 cycles) |
| Device memory (HBM model) |
8 GB (~500 cycles) |
| HiLink endpoint |
4 lanes (default) |
| Char device |
/dev/higpu0, /dev/higpu1, … |
4. Kernel driver features (higpu.ko)
Single char-device driver (src/higpu/driver/higpu.c) exposing /dev/higpuN.
4.1 ioctl interface
| ioctl |
Purpose |
HIGPU_IOC_INFO |
Query device properties (SM count, memory, IDs) |
HIGPU_IOC_ALLOC |
Allocate device memory |
HIGPU_IOC_FREE |
Free device memory |
HIGPU_IOC_MEMCPY |
Host↔device / device↔device copy |
HIGPU_IOC_LINK_STATUS |
Query HiLink endpoint status |
HIGPU_IOC_LINK_SEND |
Send a HiLink frame to a peer GPU |
HIGPU_IOC_LINK_RECV |
Receive a HiLink frame from a peer GPU |
4.2 Memory / doorbell
mmap() of BAR1 exposes the device-memory window to userspace.- BAR2 doorbell pages signal work submission; BAR0 holds MMIO control registers.
- MSI-X interrupts deliver completion and HiLink events.
5. Runtime / userspace features
Two libraries, layered CUDA-style over the driver.
5.1 libhicart.so, CUDA-Runtime-style API
| Function |
Purpose |
hicaInit / hicaShutdown |
Runtime lifecycle |
hicaGetDeviceCount |
Enumerate GPUs |
hicaGetDevice / hicaSetDevice |
Current device selection |
hicaGetDeviceProperties |
Device capability query |
hicaMalloc / hicaFree |
Device memory management |
hicaMemcpy |
Host↔device / device↔device transfers |
hicaDeviceSynchronize |
Barrier / completion wait |
hicaSgemm |
Single-precision GEMM primitive |
hicaGetErrorString |
Error decoding |
5.2 libhi.so, low-level driver shim
| Function |
Purpose |
hi_open / hi_close |
Open/close /dev/higpuN |
hi_get_device_count |
Device enumeration |
hi_query_info |
HIGPU_IOC_INFO wrapper |
hi_alloc / hi_free |
HIGPU_IOC_ALLOC / FREE wrappers |
hi_memcpy |
HIGPU_IOC_MEMCPY wrapper |
hi_mmap / hi_munmap |
BAR1 device-memory mapping |
hi_status_str |
Status decoding |
6. Compute backends & dispatch
Kernels are implemented behind a hica_compute_ops vtable; the loader picks a
backend at runtime.
| Host ISA |
Backend |
Source |
Vector width |
| x86-64 |
AVX-512 |
lib/compute/x86_avx512/ |
512-bit |
| x86-64 |
AVX2 |
lib/compute/x86_avx2/ |
256-bit |
| Portable |
scalar |
lib/compute/scalar/ |
reference/fallback |
Loader: lib/compute/loader/loader.c. Auto-selects the best backend
(AVX-512 > AVX2 > scalar). Environment overrides:
| Variable |
Effect |
HICA_COMPUTE_BACKEND |
Force a specific backend |
HICA_COMPUTE_LIST |
List available backends |
HICA_COMPUTE_VERBOSE |
Verbose selection logging |
7. GPU-to-GPU peer copy flow
sequenceDiagram
autonumber
participant App_A as GPU app (vm-a)
participant Cart_A as libhicart (vm-a)
participant Higpu_A as higpu.ko (vm-a)
participant HiLink as higpu-link-switchd
participant Higpu_B as higpu.ko (vm-b)
participant App_B as GPU app (vm-b)
App_A->>Cart_A: peer copy (dst_gpu=1)
Cart_A->>Higpu_A: ioctl HIGPU_IOC_LINK_SEND
Higpu_A->>HiLink: 12B header + payload {type=DATA, src=0, dst=1}
HiLink->>HiLink: FDB lookup by dst_gpu
HiLink->>Higpu_B: framed payload
Higpu_B-->>App_B: peer data visible in dest buffer
8. Interfaces
| Interface |
Description |
| Host bus |
QEMU PCIe device |
| BAR0 |
64 KB MMIO control registers |
| BAR1 |
Device memory window (up to 16 GB, configurable) |
| BAR2 |
4 KB per-context doorbell pages |
| Char device |
/dev/higpu0, /dev/higpu1, … |
| GPU fabric |
HiLink endpoint (see HiLink) |
9. Software support
| Item |
Value |
| Runtime |
libhicart.so (CUDA Runtime-style API) |
| Low-level driver |
libhi.so |
| Compute primitives |
vector add, tiled SGEMM (AVX2 / AVX-512) |
| Tools |
hicasmi / hi-smi (device inventory + telemetry) |
| Design reference |
HiGPU Design |
| Item |
Value |
| Repo |
PacketFive/HiGPU |
| Submodule path |
src/higpu (in PacketFive/vdc) |
| Version |
v0.2.0 |
| Language |
C (GNU C) + host SIMD intrinsics |
11. Revision history
| Revision |
Date |
Notes |
| A |
2026-07-05 |
Initial datasheet |
| B |
2026-07-05 |
Added block diagram, ioctl/runtime tables, compute-backend dispatch, peer-copy flow |