Implementation status and roadmap¶
What is built, what is superseded, and what is next across hardware, firmware, CCISRT, deployment rehearsal, and emulation.
Baseline
STM32U575xxQ + LR1120
Design record rev 2026-08-13
Ground node
Pre-production complete
Current board is a bring-up vehicle
CCISRT
Runnable
Phases 1 to 2.7, 43 checks
Open gates
2
FPGA retention, power model on hardware
Node variants Deployment rehearsal
Where the programme stands
A complete pre-production TORUS-SN board was designed, generated, routed, and released to fabrication outputs on the previous architecture. The 2026-08-13 design record then set a new baseline on STM32U575xxQ and LR1120, so that board is now a bring-up vehicle rather than the production target, and the firmware port targets the new host. Sections 3 and 4 below are scoped accordingly.
01 · Status board¶
| Area | State | Status | Detail |
|---|---|---|---|
| Design baseline | STM32U575xxQ + LR1120 | Set | Design record rev 2026-08-13; two blocking gates open: FPGA retention and power model on hardware. |
| Hardware design | TORUS-SN pre-production board | Superseded | Fully generated board, routed and polished, on the previous architecture. |
| Schematic / ERC | 0 violations | Clean | Netlist mirrors the PCB by construction. |
| PCB / DRC | 19 violations, 3 unconnected | Hand finish | Mostly waivable; about 10 minutes of GUI cleanup remains on the superseded board. |
| Baseline schematic | Not started | Blocked | Blocked on the FPGA retention gate; decide before schematic freeze. |
| Firmware | Targets previous hardware revision | Port needed | Application architecture carries over; BSP and every driver binding must be ported. |
| MEG gateway | Concept and datasheet | Design study | Clustering and high availability are design targets; the node protocol is gateway-ready. |
| CCISRT layer | Runnable, phases 1 to 2.7 | Runnable | Roles, login, telemetry, BKC, controllable simulator, maps; 43 automated checks. |
| Deployment rehearsal | OpenUSD campus generator | Runnable | Portable planner plus layered AI data center campus in torus-isaac-sim. |
| Facility emulation | Virtual RF medium | Runnable | torus-emu: nodes, medium, and a MEG bridge into CCISRT. |
| Variant hardware | SN-V2 / V3 / V4 | Design brief | Architecture and BOM briefs under hw/variants/; no PCB yet. |
02 · What exists today¶
The programme has a fielded ground-node line, in-development visual layer, runnable command layer, simulation-based deployment rehearsal, and supporting emulation fabric. Concept imagery and simulation output are labelled separately.
| Line | Current state | Detail |
|---|---|---|
| Hardware | Generated board flow | hw/torus_design.py is the single source of truth for parts, nets, footprints, GPIO-to-pad mapping, net classes, and an explicit engineering-flags list. Generated schematic, generated PCB, headless routing, and polish pass are in place. |
| Hardware | Fabrication outputs | Gerbers, drill, pick-and-place, BOM CSV, schematic PDF, top and bottom SVG, populated STEP, and optional GLB export exist for the superseded board. |
| Firmware | Zephyr application skeleton | Duty-cycled main loop, watchdog, interrupt-driven wake, power-gate management, radio handler, NMEA parser, geophone ADC sampling, and digipot gain control. The architecture carries over to the new baseline; the BSP and driver bindings must be ported. |
| CCISRT | Runnable reference application | Shared event schema, ingest adapter, persistent store with replay, correlation and track fusion, capability-based roles, login, node metadata, BKC firmware upgrade and downgrade, simulator, telemetry, maps, and Electron shell. |
| Simulation | Isaac Sim deployment rehearsal | Dependency-free planner with ring placement, seismic detection model, and SVG output, plus campus-perimeter and utility-yard scenarios across four object classes, and an NVIDIA Isaac Sim scene script for the full twin. |
| Emulation | Facility emulation fabric | Virtual RF and network medium with LoRa, SDR, wired, and Wi-Fi link models including range and contention, plus node and MEG stand-ins and a bridge into the real CCISRT application. |
03 · P0 · Close the baseline¶
These items gate the first schematic on the new baseline. They replace the earlier P0 list, which was scoped to sending the superseded board to fabrication.
| # | Task | Effort |
|---|---|---|
| 0.1 | Decide the iCE40 UP5K retention gate. On power alone it should be removed: 580 inferences/hr against a ~17,900/hr breakeven. Retention requires a written non-power justification. | Design call |
| 0.2 | Close the power model on hardware: host current on the real CMSIS-NN model, regulator efficiency over cell voltage and temperature, and LR1120 RX, Wi-Fi scan, and GNSS scan current for the exact firmware modes. | Bench programme |
| 0.3 | Fix the 433 MHz matching network for the LR1120. Semtech reference designs are 868/915 MHz and do not transfer. | Hours |
| 0.4 | Confirm the EU 433 sub-band power and duty limits against current ETSI EN 300 220 before fixing the PA design. | Hours |
| 0.5 | Verify supercapacitor sizing and leakage: at least 470 mF, no more than 3 µA leakage, tested cold, after passivation, and across converter transients. | Bench |
| 0.6 | Decide the STM32U575 pin count and whether STM32U545 is taken instead, which is about 16.5% better on energy. | Design call |
| 0.7 | Baseline schematic and PCB generation once 0.1 closes. | Weeks |
Gate 0.1 remains open
The Lattice iCE40 UP5K vector-math unit is an open, gated decision. On power alone it is 31x below the inference breakeven, so retention requires a written non-power justification.
04 · P1 · Firmware on the baseline¶
The firmware and hardware gap is the programme's main debt. Existing firmware was written for earlier hardware; the task list below targets the STM32U575xxQ and LR1120 baseline directly.
| # | Task | Notes |
|---|---|---|
| 1.1 | New Zephyr board for STM32U575xxQ | Device tree, Kconfig, pinctrl, and CMake for the Cortex-M33 host; TrustZone partitioning decision. |
| 1.2 | LR1120 driver integration | LoRa plus GNSS scan plus Wi-Fi AP scan; RFSW pins drive the PE4259 and GNSS LNA directly and must not be mapped to host GPIO. |
| 1.3 | T5848 acoustic path | I2S stereo capture, AAD threshold configuration over the one-wire THSEL protocol, and the 1.8 V rail gate. |
| 1.4 | ADS1220 seismic path | SPI driver, power gating between events, and MCP4017 threshold set into the on-die comparator. |
| 1.5 | LPBAM low-power sampling | Autonomous ADC4 capture with the core in Stop 2, which is the mechanism the power model assumes. |
| 1.6 | Wake paths | On-die COMP1/COMP2 seismic wake, T5848 WAKE pin, RTC alarm, and LoRa wake-on-radio, all verified against real hardware. |
| 1.7 | Inference integration | STM32Cube AI Studio generated INT8 model with CMSIS-NN kernels linked into the image; bit-exact vectors from the quantized export. |
| 1.8 | Fuel gauge and telemetry | BQ35100-class coulomb counting; Li-SOCl2 voltage is too flat for voltage-based gauging. |
| 1.9 | Profile engine | Stealth, standard, patrol, alert, and lockdown profiles applied as rail and duty-cycle policy, reconfigurable over LoRa downlink. |
05 · P2 · System and housekeeping¶
| # | Task | Notes |
|---|---|---|
| 2.1 | TORUS-MEG gateway detailed design and build | Take the datasheet concept to schematic and PCB; implement cluster membership, leader election, and HA failover. |
| 2.2 | Enclosure design | Autodesk Fusion, importing the TORUS-SN STEP model. |
| 2.3 | BOM generation with manufacturer part numbers | Current BOM is value and footprint only. |
| 2.4 | Bring-up and validation plan execution | Power, peripherals, AFE calibration, LoRa range, GNSS TTFF, and sleep-current measurement. |
| 2.5 | Isaac Sim twin with terrain import and physics seismic | GIS and heightmap terrain, PhysX-based detection, visual-mast sensors. |
| 2.6 | SN-V2 SDR carrier hardware design | Design brief done; Zynq plus AD9363 phase-1 carrier stacked on the V1 board; no schematic or PCB yet. |
| 2.7 | SN-V3 wired optical hardware design | Design brief done; host swap for RMII EMAC plus 100BASE-FX PHY, or ADIN1110 T1L fallback. |
| 2.8 | SN-V4 transducer interlock daughterboard | Design brief done; hardware three-condition interlock, fail-safe de-energized. |
| 2.9 | CCISRT production hardening | Real identity provider, database-backed persistence, packaged desktop and mobile installers, code signing. |
| 2.10 | Native node in torus-emu |
Build the real Zephyr firmware onto the emulated virtual medium via radio_virtual.c. |
06 · Toolchain reference¶
| Piece | Location / command |
|---|---|
| KiCad 10 | /opt/kicad, wrappers kpython and kcli.sh via setup-kicad10.sh. |
| Full hardware build | hw/build.sh (REUSE_SES=1 skips about 3 minutes of routing). |
| Best-of-N release | hw/release.sh. |
| Schematic + BOM | hw/build_sch.sh. |
| Firmware build | west build -b torus_sn .. |
| CCISRT app | cd torus-ccisrt && npm start. |
| Isaac Sim planner | cd torus-isaac-sim && python run_sim.py --scenario .... |
| Facility emulation | cd torus-emu && npm run demo. |
Pipeline gotchas already solved
These are encoded in the scripts; do not fight them. Zone fill must run as a
subprocess on the saved board. kicad-cli exports without refilling zones.
Freerouting hangs on stacked pre-placed vias. Several library footprints ship
board-blanketing antenna keepouts that must be stripped.